1. Field of the Invention
The present invention relates to the field of semiconductor packaging, and, more particularly, to the use of conductive vias in semiconductor packages.
2. Description of the Related Art
In recent years, through silicon via (TSV) has become an increasingly popular technique in the field of 3-D semiconductor packaging. In TSV, chips can be stacked on top of one another, and connected using conductive vias which are vertical pathways of interconnects that run through the chips.
Conventionally, a silicon substrate will include a plurality of through holes in which the conductive vias are formed. To avoid placing conductive metal directly on the silicon, each of the conductive vias includes an insulation layer on the sidewall and conductive metal is disposed within the hole. However, problems can occur if the insulation layer is not the proper thickness. For example, if the insulation layer is too thick, it may expand due to heat to such an extent that it interferes with a redistribution layer (RDL). Furthermore, various problems can occur if the silicon substrate is not of an optimal thickness.